LIBRARY IEEE; 			
USE IEEE.STD_LOGIC_1164.ALL;
--USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.STD_LOGIC_UNSIGNED.ALL;

USE WORK.TYPES.ALL;

entity IF_ID is
    port(
        clock,reset	    : IN  STD_LOGIC;
        NextPc_in       : IN  MEMADDR;
        Instruct_in  : IN  INSTRUCTION;
        NextPc_out      : OUT MEMADDR;
        Instruct_out : OUT INSTRUCTION
    );
end IF_ID;

architecture pipe of IF_ID is
begin
    process (clock)
    begin
        if rising_edge(clock) then
            NextPc_out      <= NextPc_in;
            Instruct_out <= Instruct_in;
        end if;
    end process;
end pipe;

